A desire to decrease the time required to configure a PLD has led to efforts in speeding up the configuration clock on the PLD that derives configuration. In most instances, the configuration clock is provided by a configuration device that transfers a programming object file to the PLD. Most configuration clocks provided by configuration devices are at a fixed clock frequency.
Some resources on the PLD, however, may have constraints that prevent them from being configured at higher frequencies. As a result, these slower resources dictated the maximum frequency of configuration. In instances where the resources requiring a slower rate of configuration represent a small subset of the configurable resources on a PLD, slowing the frequency for all the configuration of all the resources on the PLD is highly inefficient.
Approaches where configuration devices selectively changed configuration clocks in response to whether data being transmitted corresponded to the programming of slower or faster resources required significant complexity to be added to the clocking generation components in the configuration devices. Furthermore, approaches proposed to decrease the configuration time of the PLD by modifying the configuration hardware on the PLD to reduce the constraints on the slower resources proved to be costly.
Thus, what is need is a method and apparatus for supporting variable speed configuration hardware in PLD that may be used to program resources available on the PLD at different rates that is efficient and cost effective.